On-Chip Structure for Protecting Integrated Circuits from Electrostatic Discharge (ESD)

Technology #30565

Questions about this technology? Ask a Technology Manager

Download Printable PDF

Image Gallery
Schematic for complete ESD setup of this inventionTop-view of the layout design for uniform distribution of the ESD current in the device
Juin Liou, Ph.D.
Javier Salcedo
Patent Protection

On-chip structure for electrostatic discharge (ESD) protection

US Patent 7,202,114 B2

On-chip structure for electrostatic discharge (ESD) protection

US Patent 7,601,991 B2

The apparatus and method for a tunable, bidirectional high holding low voltage, silicon controlled rectifier which can provide latch-up free on-chip electrostatic discharge protection

The increasing prominence of microminiaturization in the semiconductor industry has given rise to integrated circuits with reliability and robustness issues due to their vulnerability to electrostatic discharge (ESD). This is a significant problem since the current produced by an ESD is capable of destroying microchips. Several attempts have been made to design and build on-chip structures to protect integrated circuits (IC) from the random transient high voltages caused by ESD. Yet, few are capable of providing effective and efficient protection against ESD without latch-up. To address these issues, generally one of two alternative solutions is utilized. The first involves using additional components which adds complexity and uses up additional area, possibly resulting in increased leakage current and parasitic capacitance. The second involves using empirical modification of the lateral structure of the Silicon Controlled Rectifier (SCR), but this approach is time consuming and has limited applicability.

Technical Details

UCF scientists have developed a novel SCR-based structure for ESD protection that overcomes these complications. Using two complementary n-type and p-type versions designed to enable a tunable holding voltage facilitates robust, versatile and efficient ESD protection that utilizes very little space on the chip.


  • Efficient electrostatic discharge protection
  • Occupies minimal space
  • Tunable holding voltage allowing for accurate control
  • Flexible enough for a variety of applications
  • Eliminates the need for numerous ESD protection devices, thus reducing parasitic effects


  • Protecting integrated circuits where I/O signal swing can be either within or below the circuit’s range of bias
  • Signal processing microchips
  • Communication transceivers
  • On-chip ESD protection of digital and analog circuits
  • Protection of communication ports against demanding ESD events

Additional Technology Numbers: 31110