Reliable ESD Protection Device and Method for Advanced Sub-micron CMOS Technologies

Technology #30567

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Schematic for I/0 ground-referenced ESD protection and supply clamp
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Researchers
Juin Liou, Ph.D.
Javier Salcedo
Managed By
Andrea Adkins
Assistant Director 407.823.0138
Patent Protection

Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply

US Patent 7,285,828 B2

Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply

US Patent 7,479,414 B2
Publications
Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications
IEEE Transactions on Electron Devices, Vol. 54, issue 4, April 2007, pp. 822-832
Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies
IEEE Transactions on Electron Devices, Vol. 52, Issue 12, December 2005, pp. 2682-2689.

A tunable, gateless, versatile, space-efficient, and reliable ESD protection device and method for a more robust implementation of ESD protection systems, in advanced sub-micron CMOS technologies

For many years, the semiconductor industry has employed complementary metal oxide semiconductor (CMOS) technology to manufacture reliable integrated circuits (IC) at low cost. This technology is continually evolving to include production of smaller and faster devices which can be used in very large scale integration (VLSI) systems. Some of the existing electrostatic discharge (ESD) protection schemes can be migrated and still be effective in the new CMOS technologies. However, there is no guarantee that previously developed ESD solutions will continue to perform reliably when they are scaled down or resized. Actually, some ESD models tend to become more sensitive in the new CMOS technologies. One effort to address this has been to let the ESD protection module occupy more space on the chip. Unfortunately, this does not guarantee improved performance. Another measure employed to overcome this limitation is the use of devices such as silicon controlled rectifiers (SCRs), in which the current-voltage shows voltage snapback during ESD. This facilitates the design of smaller ESD protection systems while reducing leakage current during normal operation. However, the trigger voltage is very high increasing the possibility for severe damage to the sub-micron core circuit before the protection device triggers. Low voltage SCRs are used to deal with this, but they have the disadvantage of very low holding voltages that cause latchup problems.

Technical Details

A more viable solution is a high-holding low voltage SCR (HHLVTSCR) that includes a gate to increase the speed with which a device responds to an ESD event. Such systems allow tuning of the holding voltage over a wide range while maintaining a relatively low trigger voltage. Still, their effectiveness comes into question for sub-micron CMOS applications. Systems with floating gates have been developed to correct this problem but in such systems, the conduction characteristics are unpredictably modified by the gate conditions, thus leading to unreliability. UCF researchers have developed a device that can be fabricated in the sub-micron CMOS technology, is free from the gate reliability problems and is able to pass a high level of ESD current without latchup or damage.

Benefits

  • Free from gate reliability problems
  • Tunable
  • Reliable during extreme operating conditions
  • Facilitates the ability of sub-micron CMOS technology to pass a high level of ESD current without latchup or damage

Applications

  • Semiconductors where CMOS/BiCMOS mixed signals are used
  • Mixed voltage interface peripherals such as:
    • Transceivers circuits for high speed data communication
    • Charge pump circuits
    • Voltage regulators
    • DC-DC converters
    • Power management circuits


Additional Technology Numbers: 31300